Self-aligned gate formation is desirable in integrated circuit fabrication processes. Use of self-aligned gates avoids problems caused by lithography misalignment, which become increasingly severe when critical dimensions are pushed below 0.18 microns. Critical dimension control is also improved by use of self-aligned gates.
A process for forming a self-aligned gate for a floating gate device is illustrated in FIGS. 1a-1d. 
FIG. 1a shows silicon substrate 2 with pad oxide 4 generally of thickness 100-200 Angstroms grown thereon. Silicon nitride layer 6, generally of thickness 1200-2000 Angstroms is deposited atop the pad oxide. Shallow trench etching is performed to form trenches 8, usually of depth 0.25-0.4 micron and width 0.25-0.35 micron. Following trench etch, the trenches are filled with TEOS 10 deposited at low temperature, approximately 600 C in a furnace in one atmosphere of oxygen.
Oxide CMP is performed, which removes the excess TEOS and stops on SiN 6. Overpolish removes approximately half the SiN. The remainder of the SiN is removed using wet etch techniques, then the remaining pad oxide 4 is also removed with an isotropic wet clean step. The intermediate structure following pad oxide removal is shown in FIG. 1b. 
Tunnel oxide layer 12 is formed, generally but not always by dry oxidation and having a thickness of 80-120 Angstroms, leaving recessed region 14 of depth between 500 and 1500 Angstroms. Polysilicon layer 16 of thickness between 600 and 1800 Angstroms, depending on the depth of recessed region 14, is next deposited. The intermediate structure after deposition of poly layer 16 is shown in FIG. 1c. Finally, Chemical Mechanical Polishing (CMP) is performed using a slurry having high polysilicon-to-silicon dioxide selectivity to remove the polysilicon atop the trench oxide 10, leaving self-aligned polysilicon gate 18. FIG. 1d shows the self-aligned gate structure following CMP of polysilicon.
The aforementioned self-aligned poly gate process using poly CMP has great potential for improving density of flash memory circuits, but has not been successfully implemented in manufacturing of flash memory due to associated problems.
In order to assure complete removal of the polysilicon atop filled trenches 8, overpolish of the polysilicon is required. A problem in CMP, particularly during overpolish, is known as recession or dishing, which is illustrated in FIG. 2. Uneven wafer surface 20 has recessed regions 22 and 24, region 24 having much larger surface area than region 22. Deposited layer 26 is polished off of the surface, but in the center 28 of large surface area region 24 the surface of the polished deposited layer 26 is at a lower level than at the edge 29 of region 24 or in small surface area region 22.
The dishing effect can cause severe problems during the formation of a memory cell array using the aforementioned self-aligned poly gate process. In the peripheral area of a flash memory chip, there are some active silicon regions having large feature size, e.g., large transistors for signal input/output ports, capacitors, etc. A typical flash memory chip includes 70-75% of the area as the flash memory array, with the remaining 25-30% of the area being the peripheral area containing the large feature control circuitry. Read, write, and erase functions are provided by the flash memory chip.
FIG. 3 illustrates the dishing problem after polysilicon CMP. Core region 30 of the memory cell array has small feature size, i.e., less than 3 microns, with the majority of devices having critical dimensions below 0.3 microns (usually 0.24-0.3 microns), and therefore little problem with dishing. However, peripheral region 31 having large feature size, i.e., as large as 100 microns or greater, evidences considerable dishing of the polysilicon 32, yielding very thin polysilicon in the center of feature 33, or in the worst case complete removal of the polysilicon in the center. This can have serious consequences. In the formation of flash memory circuits, following the polysilicon polish step, an Oxide-Nitride-Oxide (ONO) interpoly layer is deposited atop the wafer, and subsequently etched off the peripheral devices, which are standard CMOS devices rather than the insulated gate devices found in the central memory region of the flash memory chip, and which do not employ the ONO layer. The ONO etch is followed by stripping of the polysilicon for the large feature size peripheral CMOS devices. If during poly CMP the polysilicon is completely removed over portions of large feature size active regions, as described above when severe dishing occurs, the ONO etch will etch through tunnel oxide layer 12, and the subsequent polysilicon strip will etch into the underlying silicon substrate 2, causing serious damage to the devices. In addition, during ONO overetch in the peripheral regions, the trench isolation oxide may be significantly thinned. In some cases, the seam in the trench oxide might be opened or enlarged, which may have negative impact on device performance.